Designing computer chips is a complex process, traditionally requiring specialized expertise in hardware description languages like Verilog. But what if we could automate this process, making chip design as accessible as writing software? Recent research explores the potential of large language models (LLMs), the same technology behind AI chatbots, to revolutionize how we build hardware. Early attempts to directly generate Verilog code from LLMs showed promise but struggled to consistently produce functionally correct designs. This new research proposes a two-step approach. Instead of directly generating Verilog, LLMs create C++ code designed for High-Level Synthesis (HLS). HLS then translates this C++ code into Verilog. This method leverages the strengths of LLMs in software code generation while relying on mature HLS tools for hardware conversion. The results are impressive. Using a benchmark suite of hardware design problems and evaluating several leading LLMs, the researchers found a significant boost in accuracy compared to direct Verilog generation. One of the tested models, Claude 3.5 Sonnet, achieved an impressive 86% success rate in generating correct Verilog using this two-stage pipeline. While this approach shows exciting potential, challenges remain. The research highlighted difficulties LLMs face in certain tasks, such as simplifying logic circuits represented by Karnaugh maps. These limitations point to areas for future research and improvement. This new method of using LLMs and HLS combined offers a glimpse into a future where describing a hardware design in natural language could automatically generate the corresponding chip design, opening up hardware development to a wider range of innovators.