Imagine telling a computer, in plain English, to design a complex electronic circuit, and it just does it. That's the tantalizing promise of using Large Language Models (LLMs) for hardware design. While LLMs have shown impressive abilities in generating code for common programming languages like Python or Java, their application in hardware design languages like VHDL, crucial for describing the structure and behavior of electronic circuits, is relatively unexplored. A new research paper introduces VHDL-Eval, a specialized framework designed to evaluate the performance of LLMs in generating VHDL code. This framework includes a collection of VHDL coding problems, along with self-verifying tests to rigorously check the correctness of the AI-generated solutions. Why is this important? Because designing hardware is a complex and time-consuming process. Automating parts of this process with AI could significantly speed up development and free up engineers to focus on more creative tasks. The research focuses on converting Verilog, another hardware design language, problems into VHDL, and using publicly available resources to build up a diverse set of problems. Then, it tests how well several leading LLMs can generate VHDL code that solves these problems. The results reveal a significant challenge: while LLMs show some promise, they are not yet proficient in generating complex, functional VHDL code. This highlights the need for more focused research and development to make these AI models truly useful for hardware designers. Techniques like In-Context Learning, where the LLM is given examples of correct code to learn from, and Parameter-Efficient Fine-Tuning, which adjusts the LLM’s internal settings to better suit the specific task, show some potential for boosting performance. The journey to AI-powered hardware design is just beginning. Overcoming the current limitations could revolutionize the way electronic systems are designed and pave the way for more sophisticated and innovative hardware solutions.